Design and Implementation of a Bootstrap-based Sample and Hold Circuit for SAR ADC Applications

The resolution and conversion speed of an Analog to Digital converter (ADCs) strongly depends on how efficiently Sampling Hold (S&H) circuit handles the amplitude skewing input analog signal. In this article, a novel S&H has been proposed handle errors produced because skewing. This two different paths for sampling holds process avoids non-ideal effects seen in most recent literature. portable applications, restrictions available power importance quality digital data are taken as challenge. To make SAR-ADC more efficient, all blocks should be designed with low-power techniques. Here, sample hold block need optimized level, operate supply 3.3V, implemented SCL 0.18µm process, operating at rate 10MHz 0.425mW.